URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 100

Rev	Log message	Author	Age	Path
80	renamed to version 1.1 to follow the versioning system	JonasDC	4054d 20h	/
79	Tag for version 1.3 (with new ram style	JonasDC	4054d 20h	/
78	updated documentation with new RAM style information	JonasDC	4054d 20h	/
77	found fault in code, now synthesizes normally	JonasDC	4060d 18h	/
76	testbench update	JonasDC	4063d 05h	/
75	made rw_address a vector of a fixed width	JonasDC	4063d 05h	/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4066d 01h	/
73	updated plb interface, mem_style and device generics added	JonasDC	4067d 00h	/
72	deleted old resources	JonasDC	4068d 00h	/
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4068d 00h	/