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URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

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Rev	Log message	Author	Age	Path
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4195d 18h	/
16	package with modified generic parameter for register_n	JonasDC	4196d 07h	/
15	changed generic for register width from n to width for consistency	JonasDC	4196d 07h	/
14	changed comments, file is now according to OC design rules	JonasDC	4196d 08h	/
13	added some descriptive comments and added check for incorrect value's of width and block_width. File is now according to OC design rules	JonasDC	4196d 08h	/
12	updated comments, file is now completely according to design rules	JonasDC	4196d 08h	/
11	simulation output folder	JonasDC	4196d 10h	/
10	changed signal input port names to correct name	JonasDC	4196d 13h	/
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4196d 13h	/
8	added descriptive comments	JonasDC	4196d 15h	/
7	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4196d 15h	/
6	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4196d 16h	/
5	not needed on svn, is generated by testbench	JonasDC	4196d 16h	/
4	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4196d 17h	/
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4197d 07h	/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4201d 13h	/
1	The project and the structure was created	root	4203d 13h	/

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