OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 34

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 3788d 05h /
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 3788d 08h /
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 3788d 09h /
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 3788d 14h /
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 3788d 14h /
29 added software for generation of test input for the tesbenches JonasDC 3789d 04h /
28 updated makefile for new pipeline sources JonasDC 3789d 04h /
27 test input values for multiplier_tb JonasDC 3789d 04h /
26 testbench for only the montgommery multiplier JonasDC 3789d 04h /
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline
JonasDC 3789d 04h /
24 changed names of top-level module to mod_sim_exp_core JonasDC 3792d 13h /
23 added descriptive comments JonasDC 3792d 14h /
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 3795d 08h /
21 changed x_i signal to xi JonasDC 3796d 16h /
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules
JonasDC 3796d 16h /
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic
JonasDC 3801d 11h /
18 updated stages with comments and renamed some signals for consistency JonasDC 3802d 11h /
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 3802d 16h /
16 package with modified generic parameter for register_n JonasDC 3803d 05h /
15 changed generic for register width from n to width for consistency JonasDC 3803d 05h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2023 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.