Subversion Repositories mod_sim_exp

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Rev Log message Author Age Path
24 changed names of top-level module to mod_sim_exp_core JonasDC 4281d 23h /
23 added descriptive comments JonasDC 4282d 00h /
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4284d 18h /
21 changed x_i signal to xi JonasDC 4286d 01h /
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules
JonasDC 4286d 02h /
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic
JonasDC 4290d 21h /
18 updated stages with comments and renamed some signals for consistency JonasDC 4291d 20h /
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4292d 01h /
16 package with modified generic parameter for register_n JonasDC 4292d 14h /
15 changed generic for register width from n to width for consistency JonasDC 4292d 14h /

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