OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 51

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
51 true dual port ram for xilinx JonasDC 4055d 04h /
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx
JonasDC 4055d 04h /
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.
JonasDC 4066d 23h /
48 Tag of the starting version of the project JonasDC 4067d 00h /
47 added documentation for the IP core. JonasDC 4135d 04h /
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4135d 04h /
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4135d 04h /
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4138d 22h /
43 made the core parameters generics JonasDC 4138d 22h /
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4145d 06h /
41 removed deprecated files from version control JonasDC 4145d 06h /
40 adjusted core instantiation to new core module name JonasDC 4153d 10h /
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 4153d 21h /
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4154d 02h /
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 4157d 23h /
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.
JonasDC 4158d 20h /
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes
JonasDC 4158d 22h /
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4158d 23h /
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4159d 02h /
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4159d 03h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.