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Rev	Log message	Author	Age	Path
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4076d 21h	/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4076d 22h	/
58	made fifo full a warning	JonasDC	4079d 22h	/
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4079d 22h	/
56	this is a branch to test performance of a new style of ram	JonasDC	4080d 01h	/
55	updated resource usage in comments	JonasDC	4080d 21h	/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4080d 21h	/
53	correctly inferred ram for altera dual port ram	JonasDC	4081d 04h	/
52	correct inferring of blockram, no additional resources.	JonasDC	4081d 04h	/
51	true dual port ram for xilinx	JonasDC	4081d 05h	/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4081d 05h	/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4093d 00h	/
48	Tag of the starting version of the project	JonasDC	4093d 00h	/
47	added documentation for the IP core.	JonasDC	4161d 05h	/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4161d 05h	/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4161d 05h	/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4164d 23h	/
43	made the core parameters generics	JonasDC	4164d 23h	/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4171d 06h	/
41	removed deprecated files from version control	JonasDC	4171d 06h	/
40	adjusted core instantiation to new core module name	JonasDC	4179d 10h	/
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4179d 22h	/
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4180d 03h	/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4184d 00h	/
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4184d 20h	/
35	new test values, 1st exponentiation gives error on result with new pipeline commit for test purposes	JonasDC	4184d 23h	/
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4185d 00h	/
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4185d 03h	/
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4185d 04h	/
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4185d 09h	/

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