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Rev Log message Author Age Path
70 updated testbench for use with new core parameters
updated makefile, added new sources
JonasDC 3616d 19h /
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 3616d 19h /
68 branch no longer needed JonasDC 3616d 22h /
67 added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. JonasDC 3616d 22h /
66 added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools.
JonasDC 3616d 23h /
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package
JonasDC 3624d 14h /
64 added synthesis reports of xilinx and altera JonasDC 3624d 20h /
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 3624d 20h /
62 not used anymore JonasDC 3624d 23h /
61 updated comments, added optional altera constraint JonasDC 3624d 23h /
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.
JonasDC 3627d 13h /
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)
JonasDC 3627d 13h /
58 made fifo full a warning JonasDC 3630d 14h /
57 new fifo design, is now generic (verified with altera and xilinx) and uses block ram JonasDC 3630d 14h /
56 this is a branch to test performance of a new style of ram JonasDC 3630d 16h /
55 updated resource usage in comments JonasDC 3631d 13h /
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 3631d 13h /
53 correctly inferred ram for altera dual port ram JonasDC 3631d 20h /
52 correct inferring of blockram, no additional resources. JonasDC 3631d 20h /
51 true dual port ram for xilinx JonasDC 3631d 21h /
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx
JonasDC 3631d 21h /
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.
JonasDC 3643d 16h /
48 Tag of the starting version of the project JonasDC 3643d 16h /
47 added documentation for the IP core. JonasDC 3711d 21h /
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3711d 21h /
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3711d 21h /
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 3715d 14h /
43 made the core parameters generics JonasDC 3715d 14h /
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 3721d 22h /
41 removed deprecated files from version control JonasDC 3721d 22h /

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