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URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

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Rev Log message Author Age Path
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx
JonasDC 3631d 21h /
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.
JonasDC 3643d 16h /
48 Tag of the starting version of the project JonasDC 3643d 17h /
47 added documentation for the IP core. JonasDC 3711d 21h /
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3711d 21h /
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3711d 21h /
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 3715d 15h /
43 made the core parameters generics JonasDC 3715d 15h /
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 3721d 23h /
41 removed deprecated files from version control JonasDC 3721d 23h /

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