URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 70

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4067d 09h	/
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4067d 09h	/
68	branch no longer needed	JonasDC	4067d 11h	/
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4067d 12h	/
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4067d 12h	/
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4075d 04h	/
64	added synthesis reports of xilinx and altera	JonasDC	4075d 09h	/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4075d 09h	/
62	not used anymore	JonasDC	4075d 12h	/
61	updated comments, added optional altera constraint	JonasDC	4075d 12h	/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4078d 02h	/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4078d 03h	/
58	made fifo full a warning	JonasDC	4081d 03h	/
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4081d 03h	/
56	this is a branch to test performance of a new style of ram	JonasDC	4081d 06h	/
55	updated resource usage in comments	JonasDC	4082d 02h	/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4082d 03h	/
53	correctly inferred ram for altera dual port ram	JonasDC	4082d 09h	/
52	correct inferring of blockram, no additional resources.	JonasDC	4082d 10h	/
51	true dual port ram for xilinx	JonasDC	4082d 10h	/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories mod_sim_exp

[/] - Rev 70

Filtering Options