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Subversion Repositories mod_sim_exp

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Rev	Log message	Author	Age	Path
97	changes in makefile, and fifo's are now also in mod_sim_exp library	JonasDC	3934d 17h	/
96	minor makefile update	JonasDC	3935d 17h	/
95	new control logic for the core, allow for greater frequencies for the multiplier. changes: - autorun_cntrl: the bit selection for the exponents is now implemented with a shift register in stead of a mux. credits to Geoffrey Ottoy for new design structure. - mont_cntrl: gave the databus from and to the RAM more time to settle. data now has 3 clocks to get to its destination.	JonasDC	3935d 17h	/
94	BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include: - changed RAM and memory to support different clocks - new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org) - parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers) - added logic for control signals to cross from one clock domain to another - updated testbenches and interfaces accordingly - added log of synthesis of the 2 new fifo's for Xilinx	JonasDC	3948d 14h	/
93	Tag for Version 1.4 of The Modular Simulataneous Exponentiation Core. This version adds support for the AXI4-Lite bus interface.	JonasDC	3950d 19h	/
92	updated documentation with minor interrupt changes of AXI interface	JonasDC	3950d 19h	/
91	changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register.	JonasDC	3952d 22h	/
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	3954d 12h	/
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4018d 11h	/
88	small update on documentation, changed fault in axi control_reg	JonasDC	4024d 11h	/
87	updated documentation to version 1.4 core now supports the AXI4-Lite bus	JonasDC	4024d 12h	/
86	update on previous	JonasDC	4024d 12h	/
85	changed so that reset now also affects slave register	JonasDC	4024d 12h	/
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4025d 21h	/
83	now using values from mod_sim_exp_pkg instead of direct entity	JonasDC	4027d 22h	/
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4044d 18h	/
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4044d 18h	/
80	renamed to version 1.1 to follow the versioning system	JonasDC	4054d 12h	/
79	Tag for version 1.3 (with new ram style	JonasDC	4054d 12h	/
78	updated documentation with new RAM style information	JonasDC	4054d 12h	/
77	found fault in code, now synthesizes normally	JonasDC	4060d 09h	/
76	testbench update	JonasDC	4062d 20h	/
75	made rw_address a vector of a fixed width	JonasDC	4062d 20h	/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4065d 16h	/
73	updated plb interface, mem_style and device generics added	JonasDC	4066d 15h	/
72	deleted old resources	JonasDC	4067d 15h	/
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4067d 15h	/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4067d 16h	/
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4067d 16h	/
68	branch no longer needed	JonasDC	4067d 18h	/

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