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[/] [mod_sim_exp/] - Rev 100

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Rev Log message Author Age Path
80 renamed to version 1.1 to follow the versioning system JonasDC 4027d 16h /mod_sim_exp/
79 Tag for version 1.3 (with new ram style JonasDC 4027d 16h /mod_sim_exp/
78 updated documentation with new RAM style information JonasDC 4027d 16h /mod_sim_exp/
77 found fault in code, now synthesizes normally JonasDC 4033d 13h /mod_sim_exp/
76 testbench update JonasDC 4036d 00h /mod_sim_exp/
75 made rw_address a vector of a fixed width JonasDC 4036d 00h /mod_sim_exp/
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 4038d 20h /mod_sim_exp/
73 updated plb interface, mem_style and device generics added JonasDC 4039d 20h /mod_sim_exp/
72 deleted old resources JonasDC 4040d 20h /mod_sim_exp/
71 added synthesis report for altera and xilinx for the new ram.
added coregen sources for xilinx for primitive RAM
JonasDC 4040d 20h /mod_sim_exp/

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