URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 102

Rev	Log message	Author	Age	Path
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4045d 01h	/mod_sim_exp/
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4045d 01h	/mod_sim_exp/
80	renamed to version 1.1 to follow the versioning system	JonasDC	4054d 19h	/mod_sim_exp/
79	Tag for version 1.3 (with new ram style	JonasDC	4054d 19h	/mod_sim_exp/
78	updated documentation with new RAM style information	JonasDC	4054d 19h	/mod_sim_exp/
77	found fault in code, now synthesizes normally	JonasDC	4060d 16h	/mod_sim_exp/
76	testbench update	JonasDC	4063d 03h	/mod_sim_exp/
75	made rw_address a vector of a fixed width	JonasDC	4063d 03h	/mod_sim_exp/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4065d 23h	/mod_sim_exp/
73	updated plb interface, mem_style and device generics added	JonasDC	4066d 22h	/mod_sim_exp/