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[/] [mod_sim_exp/] - Rev 11

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Rev Log message Author Age Path
11 simulation output folder JonasDC 4430d 03h /mod_sim_exp/
10 changed signal input port names to correct name JonasDC 4430d 06h /mod_sim_exp/
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names
JonasDC 4430d 06h /mod_sim_exp/
8 added descriptive comments JonasDC 4430d 08h /mod_sim_exp/
7 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4430d 08h /mod_sim_exp/
6 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4430d 09h /mod_sim_exp/
5 not needed on svn, is generated by testbench JonasDC 4430d 09h /mod_sim_exp/
4 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4430d 10h /mod_sim_exp/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4431d 00h /mod_sim_exp/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4435d 06h /mod_sim_exp/
1 The project and the structure was created root 4437d 06h /mod_sim_exp/

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