URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 27

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Rev	Log message	Author	Age	Path
27	test input values for multiplier_tb	JonasDC	4186d 02h	/mod_sim_exp/
26	testbench for only the montgommery multiplier	JonasDC	4186d 02h	/mod_sim_exp/
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4186d 02h	/mod_sim_exp/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4189d 11h	/mod_sim_exp/
23	added descriptive comments	JonasDC	4189d 13h	/mod_sim_exp/
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4192d 06h	/mod_sim_exp/
21	changed x_i signal to xi	JonasDC	4193d 14h	/mod_sim_exp/
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4193d 14h	/mod_sim_exp/
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4198d 09h	/mod_sim_exp/
18	updated stages with comments and renamed some signals for consistency	JonasDC	4199d 09h	/mod_sim_exp/
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4199d 14h	/mod_sim_exp/
16	package with modified generic parameter for register_n	JonasDC	4200d 03h	/mod_sim_exp/
15	changed generic for register width from n to width for consistency	JonasDC	4200d 03h	/mod_sim_exp/
14	changed comments, file is now according to OC design rules	JonasDC	4200d 03h	/mod_sim_exp/
13	added some descriptive comments and added check for incorrect value's of width and block_width. File is now according to OC design rules	JonasDC	4200d 03h	/mod_sim_exp/
12	updated comments, file is now completely according to design rules	JonasDC	4200d 03h	/mod_sim_exp/
11	simulation output folder	JonasDC	4200d 06h	/mod_sim_exp/
10	changed signal input port names to correct name	JonasDC	4200d 08h	/mod_sim_exp/
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4200d 08h	/mod_sim_exp/
8	added descriptive comments	JonasDC	4200d 11h	/mod_sim_exp/

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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 27

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