OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 37

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4173d 02h /mod_sim_exp
16 package with modified generic parameter for register_n JonasDC 4173d 15h /mod_sim_exp
15 changed generic for register width from n to width for consistency JonasDC 4173d 15h /mod_sim_exp
14 changed comments, file is now according to OC design rules JonasDC 4173d 16h /mod_sim_exp
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules
JonasDC 4173d 16h /mod_sim_exp
12 updated comments, file is now completely according to design rules JonasDC 4173d 16h /mod_sim_exp
11 simulation output folder JonasDC 4173d 18h /mod_sim_exp
10 changed signal input port names to correct name JonasDC 4173d 21h /mod_sim_exp
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names
JonasDC 4173d 21h /mod_sim_exp
8 added descriptive comments JonasDC 4173d 23h /mod_sim_exp

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.