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[/] [mod_sim_exp/] - Rev 51

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Rev Log message Author Age Path
51 true dual port ram for xilinx JonasDC 3640d 16h /mod_sim_exp/
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx
JonasDC 3640d 16h /mod_sim_exp/
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.
JonasDC 3652d 11h /mod_sim_exp/
48 Tag of the starting version of the project JonasDC 3652d 11h /mod_sim_exp/
47 added documentation for the IP core. JonasDC 3720d 16h /mod_sim_exp/
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3720d 16h /mod_sim_exp/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3720d 16h /mod_sim_exp/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 3724d 10h /mod_sim_exp/
43 made the core parameters generics JonasDC 3724d 10h /mod_sim_exp/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 3730d 18h /mod_sim_exp/
41 removed deprecated files from version control JonasDC 3730d 18h /mod_sim_exp/
40 adjusted core instantiation to new core module name JonasDC 3738d 22h /mod_sim_exp/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 3739d 09h /mod_sim_exp/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 3739d 14h /mod_sim_exp/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 3743d 11h /mod_sim_exp/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.
JonasDC 3744d 08h /mod_sim_exp/
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes
JonasDC 3744d 10h /mod_sim_exp/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 3744d 11h /mod_sim_exp/
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 3744d 14h /mod_sim_exp/
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 3744d 15h /mod_sim_exp/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 3744d 20h /mod_sim_exp/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 3744d 21h /mod_sim_exp/
29 added software for generation of test input for the tesbenches JonasDC 3745d 10h /mod_sim_exp/
28 updated makefile for new pipeline sources JonasDC 3745d 10h /mod_sim_exp/
27 test input values for multiplier_tb JonasDC 3745d 10h /mod_sim_exp/
26 testbench for only the montgommery multiplier JonasDC 3745d 10h /mod_sim_exp/
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline
JonasDC 3745d 10h /mod_sim_exp/
24 changed names of top-level module to mod_sim_exp_core JonasDC 3748d 19h /mod_sim_exp/
23 added descriptive comments JonasDC 3748d 21h /mod_sim_exp/
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 3751d 14h /mod_sim_exp/

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