URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 54

Rev	Log message	Author	Age	Path
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4185d 23h	/mod_sim_exp/
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4186d 01h	/mod_sim_exp/
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4186d 02h	/mod_sim_exp/
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4186d 08h	/mod_sim_exp/
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4186d 08h	/mod_sim_exp/
29	added software for generation of test input for the tesbenches	JonasDC	4186d 21h	/mod_sim_exp/
28	updated makefile for new pipeline sources	JonasDC	4186d 22h	/mod_sim_exp/
27	test input values for multiplier_tb	JonasDC	4186d 22h	/mod_sim_exp/
26	testbench for only the montgommery multiplier	JonasDC	4186d 22h	/mod_sim_exp/
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4186d 22h	/mod_sim_exp/