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[/] [mod_sim_exp/] - Rev 57

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Rev Log message Author Age Path
57 new fifo design, is now generic (verified with altera and xilinx) and uses block ram JonasDC 3456d 16h /mod_sim_exp/
56 this is a branch to test performance of a new style of ram JonasDC 3456d 19h /mod_sim_exp/
55 updated resource usage in comments JonasDC 3457d 15h /mod_sim_exp/
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 3457d 15h /mod_sim_exp/
53 correctly inferred ram for altera dual port ram JonasDC 3457d 22h /mod_sim_exp/
52 correct inferring of blockram, no additional resources. JonasDC 3457d 22h /mod_sim_exp/
51 true dual port ram for xilinx JonasDC 3457d 23h /mod_sim_exp/
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx
JonasDC 3457d 23h /mod_sim_exp/
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.
JonasDC 3469d 18h /mod_sim_exp/
48 Tag of the starting version of the project JonasDC 3469d 18h /mod_sim_exp/
47 added documentation for the IP core. JonasDC 3537d 23h /mod_sim_exp/
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3537d 23h /mod_sim_exp/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3537d 23h /mod_sim_exp/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 3541d 16h /mod_sim_exp/
43 made the core parameters generics JonasDC 3541d 16h /mod_sim_exp/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 3548d 00h /mod_sim_exp/
41 removed deprecated files from version control JonasDC 3548d 00h /mod_sim_exp/
40 adjusted core instantiation to new core module name JonasDC 3556d 04h /mod_sim_exp/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 3556d 16h /mod_sim_exp/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 3556d 21h /mod_sim_exp/

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