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[/] [mod_sim_exp/] - Rev 66

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Rev	Log message	Author	Age	Path
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4066d 21h	/mod_sim_exp/
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4074d 12h	/mod_sim_exp/
64	added synthesis reports of xilinx and altera	JonasDC	4074d 18h	/mod_sim_exp/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4074d 18h	/mod_sim_exp/
62	not used anymore	JonasDC	4074d 21h	/mod_sim_exp/
61	updated comments, added optional altera constraint	JonasDC	4074d 21h	/mod_sim_exp/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4077d 11h	/mod_sim_exp/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4077d 11h	/mod_sim_exp/
58	made fifo full a warning	JonasDC	4080d 12h	/mod_sim_exp/
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4080d 12h	/mod_sim_exp/
56	this is a branch to test performance of a new style of ram	JonasDC	4080d 14h	/mod_sim_exp/
55	updated resource usage in comments	JonasDC	4081d 11h	/mod_sim_exp/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4081d 11h	/mod_sim_exp/
53	correctly inferred ram for altera dual port ram	JonasDC	4081d 18h	/mod_sim_exp/
52	correct inferring of blockram, no additional resources.	JonasDC	4081d 18h	/mod_sim_exp/
51	true dual port ram for xilinx	JonasDC	4081d 19h	/mod_sim_exp/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4081d 19h	/mod_sim_exp/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4093d 14h	/mod_sim_exp/
48	Tag of the starting version of the project	JonasDC	4093d 14h	/mod_sim_exp/
47	added documentation for the IP core.	JonasDC	4161d 19h	/mod_sim_exp/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4161d 19h	/mod_sim_exp/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4161d 19h	/mod_sim_exp/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4165d 12h	/mod_sim_exp/
43	made the core parameters generics	JonasDC	4165d 12h	/mod_sim_exp/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4171d 20h	/mod_sim_exp/
41	removed deprecated files from version control	JonasDC	4171d 20h	/mod_sim_exp/
40	adjusted core instantiation to new core module name	JonasDC	4180d 00h	/mod_sim_exp/
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4180d 11h	/mod_sim_exp/
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4180d 17h	/mod_sim_exp/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4184d 14h	/mod_sim_exp/

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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 66

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