URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 86

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
86	update on previous	JonasDC	4019d 07h	/mod_sim_exp/
85	changed so that reset now also affects slave register	JonasDC	4019d 07h	/mod_sim_exp/
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4020d 15h	/mod_sim_exp/
83	now using values from mod_sim_exp_pkg instead of direct entity	JonasDC	4022d 16h	/mod_sim_exp/
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4039d 12h	/mod_sim_exp/
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4039d 12h	/mod_sim_exp/
80	renamed to version 1.1 to follow the versioning system	JonasDC	4049d 06h	/mod_sim_exp/
79	Tag for version 1.3 (with new ram style	JonasDC	4049d 06h	/mod_sim_exp/
78	updated documentation with new RAM style information	JonasDC	4049d 06h	/mod_sim_exp/
77	found fault in code, now synthesizes normally	JonasDC	4055d 03h	/mod_sim_exp/
76	testbench update	JonasDC	4057d 14h	/mod_sim_exp/
75	made rw_address a vector of a fixed width	JonasDC	4057d 14h	/mod_sim_exp/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4060d 11h	/mod_sim_exp/
73	updated plb interface, mem_style and device generics added	JonasDC	4061d 10h	/mod_sim_exp/
72	deleted old resources	JonasDC	4062d 10h	/mod_sim_exp/
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4062d 10h	/mod_sim_exp/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4062d 10h	/mod_sim_exp/
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4062d 10h	/mod_sim_exp/
68	branch no longer needed	JonasDC	4062d 12h	/mod_sim_exp/
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4062d 13h	/mod_sim_exp/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 86

Filtering Options