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[/] [mod_sim_exp/] [tags/] [Release_1.1/] - Rev 87

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80 renamed to version 1.1 to follow the versioning system JonasDC 4349d 23h /mod_sim_exp/tags/Release_1.1/
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.
JonasDC 4389d 23h /mod_sim_exp/tags/Release_0.1.0/
47 added documentation for the IP core. JonasDC 4458d 04h /mod_sim_exp/trunk/
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4458d 04h /mod_sim_exp/trunk/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4458d 04h /mod_sim_exp/trunk/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4461d 21h /mod_sim_exp/trunk/
43 made the core parameters generics JonasDC 4461d 21h /mod_sim_exp/trunk/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4468d 05h /mod_sim_exp/trunk/
41 removed deprecated files from version control JonasDC 4468d 05h /mod_sim_exp/trunk/
40 adjusted core instantiation to new core module name JonasDC 4476d 09h /mod_sim_exp/trunk/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 4476d 21h /mod_sim_exp/trunk/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4477d 02h /mod_sim_exp/trunk/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 4480d 23h /mod_sim_exp/trunk/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.
JonasDC 4481d 19h /mod_sim_exp/trunk/
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes
JonasDC 4481d 22h /mod_sim_exp/trunk/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4481d 23h /mod_sim_exp/trunk/
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4482d 02h /mod_sim_exp/trunk/
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4482d 03h /mod_sim_exp/trunk/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4482d 08h /mod_sim_exp/trunk/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4482d 08h /mod_sim_exp/trunk/
29 added software for generation of test input for the tesbenches JonasDC 4482d 22h /mod_sim_exp/trunk/
28 updated makefile for new pipeline sources JonasDC 4482d 22h /mod_sim_exp/trunk/
27 test input values for multiplier_tb JonasDC 4482d 22h /mod_sim_exp/trunk/
26 testbench for only the montgommery multiplier JonasDC 4482d 22h /mod_sim_exp/trunk/
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline
JonasDC 4482d 22h /mod_sim_exp/trunk/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4486d 07h /mod_sim_exp/trunk/
23 added descriptive comments JonasDC 4486d 08h /mod_sim_exp/trunk/
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4489d 02h /mod_sim_exp/trunk/
21 changed x_i signal to xi JonasDC 4490d 10h /mod_sim_exp/trunk/
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules
JonasDC 4490d 10h /mod_sim_exp/trunk/

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