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[/] [mod_sim_exp/] [tags/] [Release_1.1/] - Rev 87

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Rev	Log message	Author	Age	Path
80	renamed to version 1.1 to follow the versioning system	JonasDC	4054d 15h	/mod_sim_exp/tags/Release_1.1
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4094d 16h	/mod_sim_exp/tags/Release_0.1.0
47	added documentation for the IP core.	JonasDC	4162d 21h	/mod_sim_exp/trunk
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4162d 21h	/mod_sim_exp/trunk
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4162d 21h	/mod_sim_exp/trunk
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4166d 14h	/mod_sim_exp/trunk
43	made the core parameters generics	JonasDC	4166d 14h	/mod_sim_exp/trunk
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4172d 22h	/mod_sim_exp/trunk
41	removed deprecated files from version control	JonasDC	4172d 22h	/mod_sim_exp/trunk
40	adjusted core instantiation to new core module name	JonasDC	4181d 02h	/mod_sim_exp/trunk
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4181d 13h	/mod_sim_exp/trunk
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4181d 19h	/mod_sim_exp/trunk
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4185d 16h	/mod_sim_exp/trunk
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4186d 12h	/mod_sim_exp/trunk
35	new test values, 1st exponentiation gives error on result with new pipeline commit for test purposes	JonasDC	4186d 14h	/mod_sim_exp/trunk
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4186d 16h	/mod_sim_exp/trunk
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4186d 18h	/mod_sim_exp/trunk
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4186d 19h	/mod_sim_exp/trunk
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4187d 01h	/mod_sim_exp/trunk
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4187d 01h	/mod_sim_exp/trunk

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[/] [mod_sim_exp/] [tags/] [Release_1.1/] - Rev 87

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