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[/] [mod_sim_exp/] [tags/] [Release_1.1/] [bench/] - Rev 104

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Rev Log message Author Age Path
80 renamed to version 1.1 to follow the versioning system JonasDC 4142d 11h /mod_sim_exp/tags/Release_1.1/bench/
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.
JonasDC 4182d 12h /mod_sim_exp/tags/Release_0.1.0/bench/
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4250d 17h /mod_sim_exp/trunk/bench/
43 made the core parameters generics JonasDC 4254d 10h /mod_sim_exp/trunk/bench/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 4273d 12h /mod_sim_exp/trunk/bench/
26 testbench for only the montgommery multiplier JonasDC 4275d 11h /mod_sim_exp/trunk/bench/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4278d 20h /mod_sim_exp/trunk/bench/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4290d 12h /mod_sim_exp/trunk/bench/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4294d 18h /mod_sim_exp/trunk/bench/

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