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[/] [mod_sim_exp/] [tags/] [Release_1.1/] [doc/] [src/] [introduction.tex] - Rev 49

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49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.
JonasDC 4324d 03h /mod_sim_exp/tags/Release_1.1/doc/src/introduction.tex
47 added documentation for the IP core. JonasDC 4392d 08h /mod_sim_exp/tags/Release_1.1/doc/src/introduction.tex

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