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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.1/] [rtl/] [vhdl/] [interface/] - Rev 80

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Rev Log message Author Age Path
80 renamed to version 1.1 to follow the versioning system JonasDC 4222d 02h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.
JonasDC 4262d 03h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4330d 07h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4334d 01h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/
43 made the core parameters generics JonasDC 4334d 01h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4340d 09h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/
40 adjusted core instantiation to new core module name JonasDC 4348d 13h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4374d 08h /mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/

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