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[/] [mod_sim_exp/] [tags/] [Release_1.3/] [bench/] - Rev 87

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Rev Log message Author Age Path
79 Tag for version 1.3 (with new ram style JonasDC 4352d 15h /mod_sim_exp/tags/Release_1.3/bench/
76 testbench update JonasDC 4360d 23h /mod_sim_exp/trunk/bench/
70 updated testbench for use with new core parameters
updated makefile, added new sources
JonasDC 4365d 19h /mod_sim_exp/trunk/bench/
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4460d 20h /mod_sim_exp/trunk/bench/
43 made the core parameters generics JonasDC 4464d 13h /mod_sim_exp/trunk/bench/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 4483d 15h /mod_sim_exp/trunk/bench/
26 testbench for only the montgommery multiplier JonasDC 4485d 14h /mod_sim_exp/trunk/bench/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4488d 23h /mod_sim_exp/trunk/bench/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4500d 15h /mod_sim_exp/trunk/bench/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4504d 21h /mod_sim_exp/trunk/bench/

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