URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.5/] - Rev 104

Rev	Log message	Author	Age	Path
78	updated documentation with new RAM style information	JonasDC	4045d 17h	/mod_sim_exp/tags/Release_1.5/
77	found fault in code, now synthesizes normally	JonasDC	4051d 14h	/mod_sim_exp/tags/Release_1.5/
76	testbench update	JonasDC	4054d 01h	/mod_sim_exp/tags/Release_1.5/
75	made rw_address a vector of a fixed width	JonasDC	4054d 01h	/mod_sim_exp/tags/Release_1.5/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4056d 21h	/mod_sim_exp/tags/Release_1.5/
73	updated plb interface, mem_style and device generics added	JonasDC	4057d 20h	/mod_sim_exp/tags/Release_1.5/
72	deleted old resources	JonasDC	4058d 20h	/mod_sim_exp/tags/Release_1.5/
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4058d 20h	/mod_sim_exp/tags/Release_1.5/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4058d 20h	/mod_sim_exp/tags/Release_1.5/
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4058d 20h	/mod_sim_exp/tags/Release_1.5/