Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.5/] - Rev 104


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Rev Log message Author Age Path
78 updated documentation with new RAM style information JonasDC 4142d 01h /mod_sim_exp/tags/Release_1.5/
77 found fault in code, now synthesizes normally JonasDC 4147d 22h /mod_sim_exp/tags/Release_1.5/
76 testbench update JonasDC 4150d 09h /mod_sim_exp/tags/Release_1.5/
75 made rw_address a vector of a fixed width JonasDC 4150d 09h /mod_sim_exp/tags/Release_1.5/
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 4153d 05h /mod_sim_exp/tags/Release_1.5/
73 updated plb interface, mem_style and device generics added JonasDC 4154d 04h /mod_sim_exp/tags/Release_1.5/
72 deleted old resources JonasDC 4155d 04h /mod_sim_exp/tags/Release_1.5/
71 added synthesis report for altera and xilinx for the new ram.
added coregen sources for xilinx for primitive RAM
JonasDC 4155d 05h /mod_sim_exp/tags/Release_1.5/
70 updated testbench for use with new core parameters
updated makefile, added new sources
JonasDC 4155d 05h /mod_sim_exp/tags/Release_1.5/
69 big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. JonasDC 4155d 05h /mod_sim_exp/tags/Release_1.5/

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