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[/] [mod_sim_exp/] [trunk/] - Rev 103

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Rev Log message Author Age Path
103 Updated documentation to version 1.5 with dual-clock support JonasDC 3567d 01h /mod_sim_exp/trunk/
102 Added some extra information for the test generation software JonasDC 3567d 01h /mod_sim_exp/trunk/
101 added README file for simulation, minor update for Makefile clean target. JonasDC 3567d 05h /mod_sim_exp/trunk/
97 changes in makefile, and fifo's are now also in mod_sim_exp library JonasDC 3602d 06h /mod_sim_exp/trunk/
96 minor makefile update JonasDC 3603d 06h /mod_sim_exp/trunk/
95 new control logic for the core, allow for greater frequencies for the multiplier.
changes:
- autorun_cntrl: the bit selection for the exponents is now implemented with a shift register in stead of a mux. credits to Geoffrey Ottoy for new design structure.
- mont_cntrl: gave the databus from and to the RAM more time to settle. data now has 3 clocks to get to its destination.		 JonasDC 3603d 06h /mod_sim_exp/trunk/
94 BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx		 JonasDC 3616d 02h /mod_sim_exp/trunk/
92 updated documentation with minor interrupt changes of AXI interface JonasDC 3618d 07h /mod_sim_exp/trunk/
91 changed interrupt structure of AXI4-Lite interface. Now the interrupt has to be acknowledged by clearing the appropriate interrupt source flag in the control register. JonasDC 3620d 10h /mod_sim_exp/trunk/
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 3622d 01h /mod_sim_exp/trunk/
89 updated vhdl files so now different clock frequencies are posible for the core and bus interface. JonasDC 3685d 23h /mod_sim_exp/trunk/
88 small update on documentation, changed fault in axi control_reg JonasDC 3692d 00h /mod_sim_exp/trunk/
87 updated documentation to version 1.4
core now supports the AXI4-Lite bus		 JonasDC 3692d 01h /mod_sim_exp/trunk/
86 update on previous JonasDC 3692d 01h /mod_sim_exp/trunk/
85 changed so that reset now also affects slave register JonasDC 3692d 01h /mod_sim_exp/trunk/
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS		 JonasDC 3693d 09h /mod_sim_exp/trunk/
83 now using values from mod_sim_exp_pkg instead of direct entity JonasDC 3695d 10h /mod_sim_exp/trunk/
82 added first version of axi-lite interface and testbench for basic axi-lite operations, now under test JonasDC 3712d 06h /mod_sim_exp/trunk/
81 updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration JonasDC 3712d 06h /mod_sim_exp/trunk/
78 updated documentation with new RAM style information JonasDC 3722d 00h /mod_sim_exp/trunk/

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