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[/] [mod_sim_exp/] [trunk/] - Rev 24

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4 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4174d 15h /mod_sim_exp/trunk/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4175d 05h /mod_sim_exp/trunk/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4179d 11h /mod_sim_exp/trunk/
1 The project and the structure was created root 4181d 10h /mod_sim_exp/trunk/

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