URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] - Rev 25

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Rev	Log message	Author	Age	Path
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4187d 17h	/mod_sim_exp/trunk/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4191d 02h	/mod_sim_exp/trunk/
23	added descriptive comments	JonasDC	4191d 04h	/mod_sim_exp/trunk/
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4193d 21h	/mod_sim_exp/trunk/
21	changed x_i signal to xi	JonasDC	4195d 05h	/mod_sim_exp/trunk/
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4195d 05h	/mod_sim_exp/trunk/
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4200d 00h	/mod_sim_exp/trunk/
18	updated stages with comments and renamed some signals for consistency	JonasDC	4201d 00h	/mod_sim_exp/trunk/
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4201d 05h	/mod_sim_exp/trunk/
16	package with modified generic parameter for register_n	JonasDC	4201d 18h	/mod_sim_exp/trunk/
15	changed generic for register width from n to width for consistency	JonasDC	4201d 18h	/mod_sim_exp/trunk/
14	changed comments, file is now according to OC design rules	JonasDC	4201d 18h	/mod_sim_exp/trunk/
13	added some descriptive comments and added check for incorrect value's of width and block_width. File is now according to OC design rules	JonasDC	4201d 18h	/mod_sim_exp/trunk/
12	updated comments, file is now completely according to design rules	JonasDC	4201d 18h	/mod_sim_exp/trunk/
11	simulation output folder	JonasDC	4201d 21h	/mod_sim_exp/trunk/
10	changed signal input port names to correct name	JonasDC	4201d 23h	/mod_sim_exp/trunk/
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4201d 23h	/mod_sim_exp/trunk/
8	added descriptive comments	JonasDC	4202d 02h	/mod_sim_exp/trunk/
7	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4202d 02h	/mod_sim_exp/trunk/
6	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4202d 02h	/mod_sim_exp/trunk/
5	not needed on svn, is generated by testbench	JonasDC	4202d 02h	/mod_sim_exp/trunk/
4	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4202d 04h	/mod_sim_exp/trunk/
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4202d 18h	/mod_sim_exp/trunk/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4207d 00h	/mod_sim_exp/trunk/
1	The project and the structure was created	root	4208d 23h	/mod_sim_exp/trunk/

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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] - Rev 25

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