Rev |
Log message |
Author |
Age |
Path |
36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4180d 13h |
/mod_sim_exp/trunk/ |
35 |
new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes |
JonasDC |
4180d 15h |
/mod_sim_exp/trunk/ |
34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4180d 16h |
/mod_sim_exp/trunk/ |
33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4180d 19h |
/mod_sim_exp/trunk/ |
32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4180d 20h |
/mod_sim_exp/trunk/ |
31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4181d 01h |
/mod_sim_exp/trunk/ |
30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4181d 02h |
/mod_sim_exp/trunk/ |
29 |
added software for generation of test input for the tesbenches |
JonasDC |
4181d 15h |
/mod_sim_exp/trunk/ |
28 |
updated makefile for new pipeline sources |
JonasDC |
4181d 16h |
/mod_sim_exp/trunk/ |
27 |
test input values for multiplier_tb |
JonasDC |
4181d 16h |
/mod_sim_exp/trunk/ |
26 |
testbench for only the montgommery multiplier |
JonasDC |
4181d 16h |
/mod_sim_exp/trunk/ |
25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4181d 16h |
/mod_sim_exp/trunk/ |
24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4185d 01h |
/mod_sim_exp/trunk/ |
23 |
added descriptive comments |
JonasDC |
4185d 02h |
/mod_sim_exp/trunk/ |
22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4187d 19h |
/mod_sim_exp/trunk/ |
21 |
changed x_i signal to xi |
JonasDC |
4189d 03h |
/mod_sim_exp/trunk/ |
20 |
added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules |
JonasDC |
4189d 03h |
/mod_sim_exp/trunk/ |
19 |
updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic |
JonasDC |
4193d 22h |
/mod_sim_exp/trunk/ |
18 |
updated stages with comments and renamed some signals for consistency |
JonasDC |
4194d 22h |
/mod_sim_exp/trunk/ |
17 |
updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules |
JonasDC |
4195d 03h |
/mod_sim_exp/trunk/ |
16 |
package with modified generic parameter for register_n |
JonasDC |
4195d 16h |
/mod_sim_exp/trunk/ |
15 |
changed generic for register width from n to width for consistency |
JonasDC |
4195d 16h |
/mod_sim_exp/trunk/ |
14 |
changed comments, file is now according to OC design rules |
JonasDC |
4195d 16h |
/mod_sim_exp/trunk/ |
13 |
added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules |
JonasDC |
4195d 17h |
/mod_sim_exp/trunk/ |
12 |
updated comments, file is now completely according to design rules |
JonasDC |
4195d 17h |
/mod_sim_exp/trunk/ |
11 |
simulation output folder |
JonasDC |
4195d 19h |
/mod_sim_exp/trunk/ |
10 |
changed signal input port names to correct name |
JonasDC |
4195d 22h |
/mod_sim_exp/trunk/ |
9 |
added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names |
JonasDC |
4195d 22h |
/mod_sim_exp/trunk/ |
8 |
added descriptive comments |
JonasDC |
4196d 00h |
/mod_sim_exp/trunk/ |
7 |
Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments |
JonasDC |
4196d 00h |
/mod_sim_exp/trunk/ |