URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] - Rev 80

Rev	Log message	Author	Age	Path
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4081d 12h	/mod_sim_exp/trunk/
53	correctly inferred ram for altera dual port ram	JonasDC	4081d 19h	/mod_sim_exp/trunk/
52	correct inferring of blockram, no additional resources.	JonasDC	4081d 19h	/mod_sim_exp/trunk/
51	true dual port ram for xilinx	JonasDC	4081d 20h	/mod_sim_exp/trunk/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4081d 20h	/mod_sim_exp/trunk/
47	added documentation for the IP core.	JonasDC	4161d 20h	/mod_sim_exp/trunk/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4161d 20h	/mod_sim_exp/trunk/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4161d 20h	/mod_sim_exp/trunk/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4165d 14h	/mod_sim_exp/trunk/
43	made the core parameters generics	JonasDC	4165d 14h	/mod_sim_exp/trunk/