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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] - Rev 86

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Rev	Log message	Author	Age	Path
86	update on previous	JonasDC	4018d 13h	/mod_sim_exp/trunk/
85	changed so that reset now also affects slave register	JonasDC	4018d 14h	/mod_sim_exp/trunk/
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4019d 22h	/mod_sim_exp/trunk/
83	now using values from mod_sim_exp_pkg instead of direct entity	JonasDC	4021d 23h	/mod_sim_exp/trunk/
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4038d 19h	/mod_sim_exp/trunk/
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4038d 19h	/mod_sim_exp/trunk/
78	updated documentation with new RAM style information	JonasDC	4048d 13h	/mod_sim_exp/trunk/
77	found fault in code, now synthesizes normally	JonasDC	4054d 10h	/mod_sim_exp/trunk/
76	testbench update	JonasDC	4056d 21h	/mod_sim_exp/trunk/
75	made rw_address a vector of a fixed width	JonasDC	4056d 21h	/mod_sim_exp/trunk/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4059d 17h	/mod_sim_exp/trunk/
73	updated plb interface, mem_style and device generics added	JonasDC	4060d 17h	/mod_sim_exp/trunk/
72	deleted old resources	JonasDC	4061d 17h	/mod_sim_exp/trunk/
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4061d 17h	/mod_sim_exp/trunk/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4061d 17h	/mod_sim_exp/trunk/
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4061d 17h	/mod_sim_exp/trunk/
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4061d 20h	/mod_sim_exp/trunk/
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4061d 20h	/mod_sim_exp/trunk/
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4069d 12h	/mod_sim_exp/trunk/
64	added synthesis reports of xilinx and altera	JonasDC	4069d 17h	/mod_sim_exp/trunk/

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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] - Rev 86

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