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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] - Rev 87

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Rev	Log message	Author	Age	Path
87	updated documentation to version 1.4 core now supports the AXI4-Lite bus	JonasDC	4024d 05h	/mod_sim_exp/trunk/
86	update on previous	JonasDC	4024d 05h	/mod_sim_exp/trunk/
85	changed so that reset now also affects slave register	JonasDC	4024d 05h	/mod_sim_exp/trunk/
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4025d 14h	/mod_sim_exp/trunk/
83	now using values from mod_sim_exp_pkg instead of direct entity	JonasDC	4027d 15h	/mod_sim_exp/trunk/
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4044d 11h	/mod_sim_exp/trunk/
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4044d 11h	/mod_sim_exp/trunk/
78	updated documentation with new RAM style information	JonasDC	4054d 05h	/mod_sim_exp/trunk/
77	found fault in code, now synthesizes normally	JonasDC	4060d 02h	/mod_sim_exp/trunk/
76	testbench update	JonasDC	4062d 13h	/mod_sim_exp/trunk/
75	made rw_address a vector of a fixed width	JonasDC	4062d 13h	/mod_sim_exp/trunk/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4065d 09h	/mod_sim_exp/trunk/
73	updated plb interface, mem_style and device generics added	JonasDC	4066d 08h	/mod_sim_exp/trunk/
72	deleted old resources	JonasDC	4067d 08h	/mod_sim_exp/trunk/
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4067d 09h	/mod_sim_exp/trunk/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4067d 09h	/mod_sim_exp/trunk/
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4067d 09h	/mod_sim_exp/trunk/
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4067d 12h	/mod_sim_exp/trunk/
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4067d 12h	/mod_sim_exp/trunk/
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4075d 04h	/mod_sim_exp/trunk/
64	added synthesis reports of xilinx and altera	JonasDC	4075d 09h	/mod_sim_exp/trunk/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4075d 09h	/mod_sim_exp/trunk/
62	not used anymore	JonasDC	4075d 12h	/mod_sim_exp/trunk/
61	updated comments, added optional altera constraint	JonasDC	4075d 12h	/mod_sim_exp/trunk/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4078d 02h	/mod_sim_exp/trunk/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4078d 03h	/mod_sim_exp/trunk/
55	updated resource usage in comments	JonasDC	4082d 02h	/mod_sim_exp/trunk/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4082d 02h	/mod_sim_exp/trunk/
53	correctly inferred ram for altera dual port ram	JonasDC	4082d 09h	/mod_sim_exp/trunk/
52	correct inferring of blockram, no additional resources.	JonasDC	4082d 09h	/mod_sim_exp/trunk/

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[/] [mod_sim_exp/] [trunk/] - Rev 87

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