URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [bench/] - Rev 54

Rev	Log message	Author	Age	Path
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	3833d 16h	/mod_sim_exp/trunk/bench/
43	made the core parameters generics	JonasDC	3837d 09h	/mod_sim_exp/trunk/bench/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	3856d 11h	/mod_sim_exp/trunk/bench/
26	testbench for only the montgommery multiplier	JonasDC	3858d 10h	/mod_sim_exp/trunk/bench/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	3861d 19h	/mod_sim_exp/trunk/bench/
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	3873d 11h	/mod_sim_exp/trunk/bench/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	3877d 17h	/mod_sim_exp/trunk/bench/