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URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [bench/] - Rev 86

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Rev	Log message	Author	Age	Path
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	3810d 12h	/mod_sim_exp/trunk/bench/
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	3829d 09h	/mod_sim_exp/trunk/bench/
76	testbench update	JonasDC	3847d 11h	/mod_sim_exp/trunk/bench/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	3852d 07h	/mod_sim_exp/trunk/bench/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	3947d 08h	/mod_sim_exp/trunk/bench/
43	made the core parameters generics	JonasDC	3951d 02h	/mod_sim_exp/trunk/bench/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	3970d 03h	/mod_sim_exp/trunk/bench/
26	testbench for only the montgommery multiplier	JonasDC	3972d 03h	/mod_sim_exp/trunk/bench/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	3975d 12h	/mod_sim_exp/trunk/bench/
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	3987d 03h	/mod_sim_exp/trunk/bench/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	3991d 09h	/mod_sim_exp/trunk/bench/

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