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[/] [mod_sim_exp/] [trunk/] [bench/] - Rev 91

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Rev Log message Author Age Path
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 3926d 17h /mod_sim_exp/trunk/bench/
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 3998d 02h /mod_sim_exp/trunk/bench/
82 added first version of axi-lite interface and testbench for basic axi-lite operations, now under test JonasDC 4016d 23h /mod_sim_exp/trunk/bench/
76 testbench update JonasDC 4035d 01h /mod_sim_exp/trunk/bench/
70 updated testbench for use with new core parameters
updated makefile, added new sources
JonasDC 4039d 21h /mod_sim_exp/trunk/bench/
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4134d 22h /mod_sim_exp/trunk/bench/
43 made the core parameters generics JonasDC 4138d 15h /mod_sim_exp/trunk/bench/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 4157d 17h /mod_sim_exp/trunk/bench/
26 testbench for only the montgommery multiplier JonasDC 4159d 16h /mod_sim_exp/trunk/bench/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4163d 01h /mod_sim_exp/trunk/bench/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4174d 17h /mod_sim_exp/trunk/bench/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4178d 23h /mod_sim_exp/trunk/bench/

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