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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [bench/] [vhdl/] - Rev 47

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Rev Log message Author Age Path
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3656d 20h /mod_sim_exp/trunk/bench/vhdl/
43 made the core parameters generics JonasDC 3660d 14h /mod_sim_exp/trunk/bench/vhdl/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 3679d 15h /mod_sim_exp/trunk/bench/vhdl/
26 testbench for only the montgommery multiplier JonasDC 3681d 14h /mod_sim_exp/trunk/bench/vhdl/
24 changed names of top-level module to mod_sim_exp_core JonasDC 3684d 23h /mod_sim_exp/trunk/bench/vhdl/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 3696d 15h /mod_sim_exp/trunk/bench/vhdl/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 3700d 21h /mod_sim_exp/trunk/bench/vhdl/

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