URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [bench/] [vhdl/] - Rev 77

Rev	Log message	Author	Age	Path
76	testbench update	JonasDC	3663d 19h	/mod_sim_exp/trunk/bench/vhdl/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	3668d 14h	/mod_sim_exp/trunk/bench/vhdl/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	3763d 15h	/mod_sim_exp/trunk/bench/vhdl/
43	made the core parameters generics	JonasDC	3767d 09h	/mod_sim_exp/trunk/bench/vhdl/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	3786d 11h	/mod_sim_exp/trunk/bench/vhdl/
26	testbench for only the montgommery multiplier	JonasDC	3788d 10h	/mod_sim_exp/trunk/bench/vhdl/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	3791d 19h	/mod_sim_exp/trunk/bench/vhdl/
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	3803d 10h	/mod_sim_exp/trunk/bench/vhdl/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	3807d 16h	/mod_sim_exp/trunk/bench/vhdl/