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URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [bench/] [vhdl/] - Rev 88

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Rev	Log message	Author	Age	Path
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4026d 06h	/mod_sim_exp/trunk/bench/vhdl/
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4045d 03h	/mod_sim_exp/trunk/bench/vhdl/
76	testbench update	JonasDC	4063d 06h	/mod_sim_exp/trunk/bench/vhdl/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4068d 01h	/mod_sim_exp/trunk/bench/vhdl/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4163d 03h	/mod_sim_exp/trunk/bench/vhdl/
43	made the core parameters generics	JonasDC	4166d 20h	/mod_sim_exp/trunk/bench/vhdl/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4185d 22h	/mod_sim_exp/trunk/bench/vhdl/
26	testbench for only the montgommery multiplier	JonasDC	4187d 21h	/mod_sim_exp/trunk/bench/vhdl/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4191d 06h	/mod_sim_exp/trunk/bench/vhdl/
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4202d 21h	/mod_sim_exp/trunk/bench/vhdl/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4207d 03h	/mod_sim_exp/trunk/bench/vhdl/

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