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[/] [mod_sim_exp/] [trunk/] [bench/] [vhdl/] [mod_sim_exp_core_tb.vhd] - Rev 94

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94 BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx
JonasDC 3445d 12h /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
JonasDC 3522d 19h /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
76 testbench update JonasDC 3559d 18h /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
70 updated testbench for use with new core parameters
updated makefile, added new sources
JonasDC 3564d 14h /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 3659d 15h /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
43 made the core parameters generics JonasDC 3663d 09h /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 3682d 10h /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
24 changed names of top-level module to mod_sim_exp_core JonasDC 3687d 18h /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 3699d 10h /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 3703d 16h /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd

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