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[/] [mod_sim_exp/] [trunk/] [bench/] [vhdl/] [mod_sim_exp_core_tb.vhd] - Rev 43

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Rev Log message Author Age Path
43 made the core parameters generics JonasDC 4138d 11h /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 4157d 13h /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
24 changed names of top-level module to mod_sim_exp_core JonasDC 4162d 21h /mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4174d 12h /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4178d 18h /mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd

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