Rev |
Log message |
Author |
Age |
Path |
60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4076d 13h |
/mod_sim_exp/trunk/rtl/ |
59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4076d 13h |
/mod_sim_exp/trunk/rtl/ |
55 |
updated resource usage in comments |
JonasDC |
4080d 13h |
/mod_sim_exp/trunk/rtl/ |
54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4080d 13h |
/mod_sim_exp/trunk/rtl/ |
53 |
correctly inferred ram for altera dual port ram |
JonasDC |
4080d 20h |
/mod_sim_exp/trunk/rtl/ |
52 |
correct inferring of blockram, no additional resources. |
JonasDC |
4080d 20h |
/mod_sim_exp/trunk/rtl/ |
51 |
true dual port ram for xilinx |
JonasDC |
4080d 21h |
/mod_sim_exp/trunk/rtl/ |
50 |
added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx |
JonasDC |
4080d 21h |
/mod_sim_exp/trunk/rtl/ |
45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4160d 21h |
/mod_sim_exp/trunk/rtl/ |
44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4164d 14h |
/mod_sim_exp/trunk/rtl/ |
43 |
made the core parameters generics |
JonasDC |
4164d 14h |
/mod_sim_exp/trunk/rtl/ |
42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4170d 22h |
/mod_sim_exp/trunk/rtl/ |
41 |
removed deprecated files from version control |
JonasDC |
4170d 22h |
/mod_sim_exp/trunk/rtl/ |
40 |
adjusted core instantiation to new core module name |
JonasDC |
4179d 02h |
/mod_sim_exp/trunk/rtl/ |
39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4179d 13h |
/mod_sim_exp/trunk/rtl/ |
38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4179d 19h |
/mod_sim_exp/trunk/rtl/ |
37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4183d 16h |
/mod_sim_exp/trunk/rtl/ |
36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4184d 12h |
/mod_sim_exp/trunk/rtl/ |
34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4184d 16h |
/mod_sim_exp/trunk/rtl/ |
33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4184d 18h |
/mod_sim_exp/trunk/rtl/ |
32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4184d 19h |
/mod_sim_exp/trunk/rtl/ |
31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4185d 01h |
/mod_sim_exp/trunk/rtl/ |
30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4185d 01h |
/mod_sim_exp/trunk/rtl/ |
25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4185d 15h |
/mod_sim_exp/trunk/rtl/ |
24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4189d 00h |
/mod_sim_exp/trunk/rtl/ |
23 |
added descriptive comments |
JonasDC |
4189d 01h |
/mod_sim_exp/trunk/rtl/ |
22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4191d 19h |
/mod_sim_exp/trunk/rtl/ |
21 |
changed x_i signal to xi |
JonasDC |
4193d 02h |
/mod_sim_exp/trunk/rtl/ |
20 |
added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules |
JonasDC |
4193d 03h |
/mod_sim_exp/trunk/rtl/ |
19 |
updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic |
JonasDC |
4197d 22h |
/mod_sim_exp/trunk/rtl/ |