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[/] [mod_sim_exp/] [trunk/] [rtl/] - Rev 62

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Rev	Log message	Author	Age	Path
62	not used anymore	JonasDC	4076d 03h	/mod_sim_exp/trunk/rtl/
61	updated comments, added optional altera constraint	JonasDC	4076d 03h	/mod_sim_exp/trunk/rtl/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4078d 17h	/mod_sim_exp/trunk/rtl/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4078d 18h	/mod_sim_exp/trunk/rtl/
55	updated resource usage in comments	JonasDC	4082d 17h	/mod_sim_exp/trunk/rtl/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4082d 17h	/mod_sim_exp/trunk/rtl/
53	correctly inferred ram for altera dual port ram	JonasDC	4083d 00h	/mod_sim_exp/trunk/rtl/
52	correct inferring of blockram, no additional resources.	JonasDC	4083d 00h	/mod_sim_exp/trunk/rtl/
51	true dual port ram for xilinx	JonasDC	4083d 01h	/mod_sim_exp/trunk/rtl/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4083d 01h	/mod_sim_exp/trunk/rtl/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4163d 01h	/mod_sim_exp/trunk/rtl/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4166d 18h	/mod_sim_exp/trunk/rtl/
43	made the core parameters generics	JonasDC	4166d 18h	/mod_sim_exp/trunk/rtl/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4173d 02h	/mod_sim_exp/trunk/rtl/
41	removed deprecated files from version control	JonasDC	4173d 02h	/mod_sim_exp/trunk/rtl/
40	adjusted core instantiation to new core module name	JonasDC	4181d 06h	/mod_sim_exp/trunk/rtl/
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4181d 18h	/mod_sim_exp/trunk/rtl/
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4181d 23h	/mod_sim_exp/trunk/rtl/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4185d 20h	/mod_sim_exp/trunk/rtl/
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4186d 16h	/mod_sim_exp/trunk/rtl/

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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] - Rev 62

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