| Rev |
Log message |
Author |
Age |
Path |
| 77 |
found fault in code, now synthesizes normally |
JonasDC |
4060d 14h |
/mod_sim_exp/trunk/rtl/ |
| 75 |
made rw_address a vector of a fixed width |
JonasDC |
4063d 01h |
/mod_sim_exp/trunk/rtl/ |
| 74 |
removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. |
JonasDC |
4065d 21h |
/mod_sim_exp/trunk/rtl/ |
| 73 |
updated plb interface, mem_style and device generics added |
JonasDC |
4066d 20h |
/mod_sim_exp/trunk/rtl/ |
| 69 |
big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. |
JonasDC |
4067d 20h |
/mod_sim_exp/trunk/rtl/ |
| 67 |
added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. |
JonasDC |
4067d 23h |
/mod_sim_exp/trunk/rtl/ |
| 66 |
added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools. |
JonasDC |
4067d 23h |
/mod_sim_exp/trunk/rtl/ |
| 65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4075d 15h |
/mod_sim_exp/trunk/rtl/ |
| 63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4075d 21h |
/mod_sim_exp/trunk/rtl/ |
| 62 |
not used anymore |
JonasDC |
4075d 23h |
/mod_sim_exp/trunk/rtl/ |
| 61 |
updated comments, added optional altera constraint |
JonasDC |
4075d 23h |
/mod_sim_exp/trunk/rtl/ |
| 60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4078d 14h |
/mod_sim_exp/trunk/rtl/ |
| 59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4078d 14h |
/mod_sim_exp/trunk/rtl/ |
| 55 |
updated resource usage in comments |
JonasDC |
4082d 14h |
/mod_sim_exp/trunk/rtl/ |
| 54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4082d 14h |
/mod_sim_exp/trunk/rtl/ |
| 53 |
correctly inferred ram for altera dual port ram |
JonasDC |
4082d 20h |
/mod_sim_exp/trunk/rtl/ |
| 52 |
correct inferring of blockram, no additional resources. |
JonasDC |
4082d 21h |
/mod_sim_exp/trunk/rtl/ |
| 51 |
true dual port ram for xilinx |
JonasDC |
4082d 21h |
/mod_sim_exp/trunk/rtl/ |
| 50 |
added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx |
JonasDC |
4082d 22h |
/mod_sim_exp/trunk/rtl/ |
| 45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4162d 21h |
/mod_sim_exp/trunk/rtl/ |
| 44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4166d 15h |
/mod_sim_exp/trunk/rtl/ |
| 43 |
made the core parameters generics |
JonasDC |
4166d 15h |
/mod_sim_exp/trunk/rtl/ |
| 42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4172d 23h |
/mod_sim_exp/trunk/rtl/ |
| 41 |
removed deprecated files from version control |
JonasDC |
4172d 23h |
/mod_sim_exp/trunk/rtl/ |
| 40 |
adjusted core instantiation to new core module name |
JonasDC |
4181d 03h |
/mod_sim_exp/trunk/rtl/ |
| 39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4181d 14h |
/mod_sim_exp/trunk/rtl/ |
| 38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4181d 20h |
/mod_sim_exp/trunk/rtl/ |
| 37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4185d 17h |
/mod_sim_exp/trunk/rtl/ |
| 36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4186d 13h |
/mod_sim_exp/trunk/rtl/ |
| 34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4186d 16h |
/mod_sim_exp/trunk/rtl/ |
