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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 14

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14 changed comments, file is now according to OC design rules JonasDC 4280d 17h /mod_sim_exp/trunk/rtl/vhdl/
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules
JonasDC 4280d 17h /mod_sim_exp/trunk/rtl/vhdl/
12 updated comments, file is now completely according to design rules JonasDC 4280d 17h /mod_sim_exp/trunk/rtl/vhdl/
10 changed signal input port names to correct name JonasDC 4280d 22h /mod_sim_exp/trunk/rtl/vhdl/
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names
JonasDC 4280d 22h /mod_sim_exp/trunk/rtl/vhdl/
8 added descriptive comments JonasDC 4281d 00h /mod_sim_exp/trunk/rtl/vhdl/
7 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4281d 00h /mod_sim_exp/trunk/rtl/vhdl/
6 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4281d 01h /mod_sim_exp/trunk/rtl/vhdl/
4 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments
JonasDC 4281d 02h /mod_sim_exp/trunk/rtl/vhdl/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4281d 16h /mod_sim_exp/trunk/rtl/vhdl/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4285d 22h /mod_sim_exp/trunk/rtl/vhdl/

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