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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 30

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Rev	Log message	Author	Age	Path
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4778d 06h	/mod_sim_exp/trunk/rtl/vhdl/
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4778d 20h	/mod_sim_exp/trunk/rtl/vhdl/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4782d 05h	/mod_sim_exp/trunk/rtl/vhdl/
23	added descriptive comments	JonasDC	4782d 06h	/mod_sim_exp/trunk/rtl/vhdl/
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4785d 00h	/mod_sim_exp/trunk/rtl/vhdl/
21	changed x_i signal to xi	JonasDC	4786d 07h	/mod_sim_exp/trunk/rtl/vhdl/
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4786d 08h	/mod_sim_exp/trunk/rtl/vhdl/
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4791d 03h	/mod_sim_exp/trunk/rtl/vhdl/
18	updated stages with comments and renamed some signals for consistency	JonasDC	4792d 02h	/mod_sim_exp/trunk/rtl/vhdl/
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4792d 07h	/mod_sim_exp/trunk/rtl/vhdl/
16	package with modified generic parameter for register_n	JonasDC	4792d 20h	/mod_sim_exp/trunk/rtl/vhdl/
15	changed generic for register width from n to width for consistency	JonasDC	4792d 20h	/mod_sim_exp/trunk/rtl/vhdl/
14	changed comments, file is now according to OC design rules	JonasDC	4792d 21h	/mod_sim_exp/trunk/rtl/vhdl/
13	added some descriptive comments and added check for incorrect value's of width and block_width. File is now according to OC design rules	JonasDC	4792d 21h	/mod_sim_exp/trunk/rtl/vhdl/
12	updated comments, file is now completely according to design rules	JonasDC	4792d 21h	/mod_sim_exp/trunk/rtl/vhdl/
10	changed signal input port names to correct name	JonasDC	4793d 02h	/mod_sim_exp/trunk/rtl/vhdl/
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4793d 02h	/mod_sim_exp/trunk/rtl/vhdl/
8	added descriptive comments	JonasDC	4793d 04h	/mod_sim_exp/trunk/rtl/vhdl/
7	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4793d 04h	/mod_sim_exp/trunk/rtl/vhdl/
6	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4793d 05h	/mod_sim_exp/trunk/rtl/vhdl/

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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 30

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