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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 43

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Rev Log message Author Age Path
43 made the core parameters generics JonasDC 4157d 23h /mod_sim_exp/trunk/rtl/vhdl/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4164d 07h /mod_sim_exp/trunk/rtl/vhdl/
41 removed deprecated files from version control JonasDC 4164d 07h /mod_sim_exp/trunk/rtl/vhdl/
40 adjusted core instantiation to new core module name JonasDC 4172d 11h /mod_sim_exp/trunk/rtl/vhdl/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic		 JonasDC 4172d 23h /mod_sim_exp/trunk/rtl/vhdl/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4173d 04h /mod_sim_exp/trunk/rtl/vhdl/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4177d 01h /mod_sim_exp/trunk/rtl/vhdl/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4177d 21h /mod_sim_exp/trunk/rtl/vhdl/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4178d 01h /mod_sim_exp/trunk/rtl/vhdl/
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4178d 04h /mod_sim_exp/trunk/rtl/vhdl/
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4178d 05h /mod_sim_exp/trunk/rtl/vhdl/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4178d 10h /mod_sim_exp/trunk/rtl/vhdl/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4178d 10h /mod_sim_exp/trunk/rtl/vhdl/
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline		 JonasDC 4179d 00h /mod_sim_exp/trunk/rtl/vhdl/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4182d 09h /mod_sim_exp/trunk/rtl/vhdl/
23 added descriptive comments JonasDC 4182d 10h /mod_sim_exp/trunk/rtl/vhdl/
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4185d 04h /mod_sim_exp/trunk/rtl/vhdl/
21 changed x_i signal to xi JonasDC 4186d 11h /mod_sim_exp/trunk/rtl/vhdl/
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules		 JonasDC 4186d 12h /mod_sim_exp/trunk/rtl/vhdl/
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic		 JonasDC 4191d 07h /mod_sim_exp/trunk/rtl/vhdl/

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