OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 46

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4134d 21h /mod_sim_exp/trunk/rtl/vhdl/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4138d 15h /mod_sim_exp/trunk/rtl/vhdl/
43 made the core parameters generics JonasDC 4138d 15h /mod_sim_exp/trunk/rtl/vhdl/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4144d 23h /mod_sim_exp/trunk/rtl/vhdl/
41 removed deprecated files from version control JonasDC 4144d 23h /mod_sim_exp/trunk/rtl/vhdl/
40 adjusted core instantiation to new core module name JonasDC 4153d 03h /mod_sim_exp/trunk/rtl/vhdl/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 4153d 14h /mod_sim_exp/trunk/rtl/vhdl/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4153d 19h /mod_sim_exp/trunk/rtl/vhdl/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 4157d 16h /mod_sim_exp/trunk/rtl/vhdl/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.
JonasDC 4158d 13h /mod_sim_exp/trunk/rtl/vhdl/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4158d 16h /mod_sim_exp/trunk/rtl/vhdl/
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4158d 19h /mod_sim_exp/trunk/rtl/vhdl/
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4158d 20h /mod_sim_exp/trunk/rtl/vhdl/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4159d 01h /mod_sim_exp/trunk/rtl/vhdl/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4159d 02h /mod_sim_exp/trunk/rtl/vhdl/
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline
JonasDC 4159d 15h /mod_sim_exp/trunk/rtl/vhdl/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4163d 00h /mod_sim_exp/trunk/rtl/vhdl/
23 added descriptive comments JonasDC 4163d 02h /mod_sim_exp/trunk/rtl/vhdl/
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4165d 19h /mod_sim_exp/trunk/rtl/vhdl/
21 changed x_i signal to xi JonasDC 4167d 03h /mod_sim_exp/trunk/rtl/vhdl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.