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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 77

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Rev Log message Author Age Path
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4139d 18h /mod_sim_exp/trunk/rtl/vhdl/
43 made the core parameters generics JonasDC 4139d 18h /mod_sim_exp/trunk/rtl/vhdl/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4146d 02h /mod_sim_exp/trunk/rtl/vhdl/
41 removed deprecated files from version control JonasDC 4146d 02h /mod_sim_exp/trunk/rtl/vhdl/
40 adjusted core instantiation to new core module name JonasDC 4154d 06h /mod_sim_exp/trunk/rtl/vhdl/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic
JonasDC 4154d 18h /mod_sim_exp/trunk/rtl/vhdl/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4154d 23h /mod_sim_exp/trunk/rtl/vhdl/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline
JonasDC 4158d 20h /mod_sim_exp/trunk/rtl/vhdl/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.
JonasDC 4159d 16h /mod_sim_exp/trunk/rtl/vhdl/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4159d 20h /mod_sim_exp/trunk/rtl/vhdl/

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